1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, further detailedly relates to technique for reducing ON-state resistance without reducing the withstand voltage of a high-withstand voltage MOS transistor.
2. Description of the Related Art
Referring to the drawings, a conventional type semiconductor device, particularly P-channel type MOS transistor will be described below.
As shown in FIG. 15, a reference number 51 denotes a P-type semiconductor substrate(Psub) for example, 52 denotes an N-type well region (NW) and an LP layer 53A (composing a drift region) is formed in the N-type well region 52. Reference numbers 54A and 54B respectively denote a selective oxide film (for forming a gate oxide film) and a local oxide film (composing an element isolation film) respectively formed by LOCOS(Local Oxidation of Silicon).
A reference number 55 denotes a gate oxide film, 56 denotes a gate electrode formed so that the gate electrode ranges from the gate oxide film 55 to the selective oxide film 54A, and 57A and 58A denote an P+type source region formed so that it is adjacent to the gate electrode 56 and an P+type drain region formed in a position apart from the gate electrode 56.
The conventional type semiconductor device adopts LDD structure including the drift region (the LP layer 53A) deep diffused so that the drift region surrounds the drain region 58 to increase the withstand voltage as shown in FIG. 15.
However, there is a correlation shown in FIG. 16 between the density of the drift region (the LP layer 53A) and the withstand voltage (BVDS) between the source and the drain, therefore, the upper limit value exists for the density of the drift region (the LP layer 53A) and the resistance value of the drift region (the LP layer 53) cannot be reduced more.
Now referring to the drawings, an explanation will be given of a conventional semiconductor device, particularly an N-channel type MOS transistor. The explanation of the same structure as the above P-channel type MOS transistor will be replaced by the same reference symbols.
As seen from FIG. 17, an LN (lightly doped N-type) layer 53B which constitutes a drift region) is formed in e.g. a P type semiconductor substrate 51. Selective oxide films 54A and 54B, which are formed by LOCOS, constitute a second gate oxide film and an isolation film, respectively.
A gate electrode 56 is formed to extend over a gate oxide film 55 and the above second gate oxide film 54A. A highly doped N+ source layer 57B is formed to be adjacent to the gate electrode 56. A highly doped N+ layer drain layer 58B is formed apart from the gate electrode 56.
As shown in FIG. 17, the conventional semiconductor device described above is a single side LDD structure semiconductor device having the drift region (LN layer 53B) which is diffused deep to surround the drain region 58B in order to realize a high breakdown voltage.
In the semiconductor device having the single side LDD structure as described above, the drift region 53B which has high resistance was a cause of reducing the driving capability.
In the semiconductor device having the single side LDD structure in which a high voltage is applied to only the side of the drain region, on the side of the drain region, in order to relax the concentration of an electric field, the highly doped drain region 58B was surrounded by the lightly doped drift region (LN layer 53B), whereas only the highly doped source region 57B was present on the side of the source region.
Even with the semiconductor device having such a structure, a static breakdown voltage was not particularly problematic. However, in operation, the following problems occurred. In the bipolar structure consisting of a source region (emitter region), a substrate (base region) and a drain region (collector region), because the highly doped source region 57 is naked, the emitter region has high efficiency of carrier injection. Therefore, the substrate current Isub is so large that the bipolar transistor is likely to turn on.
Thus, since the current gain β in the bipolar transistor is high, the drain breakdown voltage in operation falls more greatly than the semiconductor device having a double side LDD structure.
In order to improve the drain breakdown voltage in operation, the substrate current Isub must be decreased. Namely, the drain field must be further decreased.
However, when the impurity concentration of the entire lightly doped drift region (LN layer 53B) is decreased for the purpose of decreasing the substrate current Isub, as shown by solid line in FIG. 18, the substrate current Isub has a double hump structure that two peaks (1) and (2) appear as the voltage Vgs increases.
In this case, where the pertinent lightly doped drift region (LN layer 53B) has a lower concentration, the first peak (1) of the substrate current Isub is low so that the drain voltage at a low Vgs is improved. On the other hand, the second peak (2) of the substrate current Isub is relatively high so that the drain voltage at a high Vgs is attenuated.
On the contrary, when the entire lightly doped drift region (LN layer 53B) is increased, as shown by one-dot chain line in FIG. 18, the substrate current Isub has a single peak at a certain voltage Vgs. This is efficient to improve the drain voltage at a high Vgs, but attenuates the drain voltage at a low Vgs.
In this way, if the impurity concentration of the entire lightly doped drift region (LN layer 53B) is decreased, the “trade-off” relationship between the drain voltage at the low Vgs and that at the high Vgs cannot be overcome.
Further, the double side LDD structure which has been commonly used decreases the current gain β so that the breakdown voltage can be certainly improved. However, a high breakdown voltage is not essentially required on the side of the source region. In this case, if the general LDD structure is adopted also on the side of the source region, it has the same distance (L) of the drift region as that on the side of the drain region. This increases the ON resistance and attenuates the driving capability.